Cypress SONOS – A Scalable Embedded Flash Technology

by Krishnaswamy Ramkumar
Cypress Semiconductor

The demand for embedded Flash memory in system-on-chip (SOC) designs has grown steeply in recent years as newer applications evolve in communications and consumer electronics. The memory content of complex SOC has increased due to increased demand on system performance. Flash memory is highly desirable in most applications to store critical data and code. However, SOC designers require a Flash memory that is easily integrated with the rest of the circuitry at a low cost. This requirement is challenging and was a barrier for the growth of SOCs with Flash memory. Conventional floating gate technology was used for embedded solutions in the older technologies (0.25 µm and 0.18 µm) but scaling it down to 130 nm and beyond has proved to be difficult and expensive. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology has been known as a Flash technology since the 1980s. However, in the past it was not very successful in competing against the floating gate technology for standalone nonvolatile memories. In recent years, with the increasing demand for embedded nonvolatile memory, SONOS, being more scalable and more compatible with the logic technology, is becoming very attractive.

A SONOS memory uses an insulating layer such as silicon nitride with traps as the charge storage layer. The traps in the nitride capture the carriers injected from the channel and retain the charge. This type of memory is also known as “Charge Trap Memory.” The heart of the SONOS technology is the SONOS FET shown in Figure 1. This is a MOS transistor with ONO stack as the gate dielectric. The ONO stack is designed to provide the required program or erase speeds and high reliability. The SONOS transistor shares many of the key process steps with the CMOS transistors. Hence, many regions of the SONOS transistor, such as source, drain, and gate, are identical to those of the CMOS transistors. This makes the process architecture of the embedded SONOS technology significantly simpler.
Figure 1. SONOS Transistor Schematic

Cypress’ SONOS technology is an embedded nonvolatile technology that integrates a highly reliable SONOS transistor into a CMOS process flow with minimum additional mask layers and minimal impact on the electrical parameters of the CMOS FETs. Cypress uses a unique process for the SONOS transistor to achieve superior reliability. With integration simpler than that of floating gate (FG) Flash, the Cypress SONOS technology can enable a faster ramp to a high yield process flow. This technology is qualified in Cypress manufacturing plants and in a foundry. The Cypress SONOS cell is highly suitable for designing and manufacturing EEPROM and embedding Flash memory into logic integrated circuits. The Cypress SONOS technology uses fewer mask layers than FG technology. It is very compatible with CMOS logic technology, which makes it ideal for embedded Flash. It is also scalable to more advanced technology nodes such as 65 nm and 45 nm.

• Fully compatible with CMOS process – Highly scalable, Single poly process flow
• Low cost integration into Logic process with fewer extra masks compared to FG
• Minimum impact on existing CMOS SOC IP due to a low thermal budget process
• No negative impact on yield since SONOS module is insensitive to front end defects
• Low test cost due to high intrinsic yield which eliminates the need for some of the tests
• Low programming voltage which results in smaller IP blocks for charge pumps
• High Reliability meeting truly Flash specifications

A key requirement for an NVM cell is reliability. The End-of-Life (EOL) Vt window is determined by the degradation caused by program/erase cycles (Endurance) and Vt decay during storage (Data retention). Cypress SONOS technology guarantees retention of 20 years after 100K cycles of Program/Erase. The reliability specifications for Cypress SONOS technology are given in Table 1.
Table 1. Reliability Specifications for SONOS Technology

The Cypress SONOS module can easily be embedded into a logic process flow or an SRAM process flow with the addition of three to five masking layers as compared to about ten in the case of floating gate flash. The integration scheme includes a dual gate oxide process, which enables the chip to be compatible with multiple supply voltages. The SONOS can also be integrated into a state-of-the-art logic process flow, which includes salicided junctions, stress layers, and Cu-low K interconnects. The integration can be done at many of the technology nodes such as 130 nm, 90 nm, or 65 nm with very few changes except for cell shrink with more aggressive design rules. The optimized thermal budget of SONOS integration ensures a negligible impact on the electrical parameters of existing CMOS devices. This is proven even on very sensitive devices in the 65 nm technology. This means that with minimal changes, all the design IP of the original CMOS platform can be used in the embedded ICs.

For more information on Cypress SONOS technology, please contact sonosinfo@cypress.com

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About the Author

Krishnaswamy Ramkumar has spent 18 years in the semiconductor industry. He has been at Cypress since 1993 and is currently a Senior Member of Technical Staff Worked on Advanced Process Integration development. He has worked on numerous technology generations from 0.50 um to 65 nm with emphasis on front end process development.